-- $Id: $
-- File name:   TX_TIMER.vhd
-- Created:     12/3/2010
-- Author:      Alyssa Welles
-- Lab Section: 4
-- Version:     1.0  Initial Design Entry
-- Description: Timer Block for the Transmitter.


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity TX_TIMER is
  port(
          CLK : in std_logic;
        RST_N : in std_logic;
          LOG : in std_logic;
 SHIFT_ENABLE : out std_logic
      );
end TX_TIMER;

architecture BEHAVIORAL of TX_TIMER is
 signal count, nextCount: std_logic_vector(3 downto 0);
begin
 StateReg : process (CLK, RST_N)
 begin
  if (RST_N = '0') then
    count <= (others => '0');
  elsif (CLK'event and CLK = '1') then
    count <= nextCount;
  end if;
 end process StateReg;

 NxStLogic : process(count, LOG)
 begin
  if count = "0111" then
    nextCount <= "0000";
  elsif LOG = '1' then 
    nextCount <= count + 1;
  else
    nextCount <= count;
  end if;
 end process NxStLogic;

 outL : process(count)
  begin
  SHIFT_ENABLE <= '0';
  CASE count is
   when "0111" => 
     SHIFT_ENABLE <= '1';
   when others => 
     SHIFT_ENABLE <= '0';
  end CASE;
 end process outL;

end BEHAVIORAL;



